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?2008 silicon storage technology, inc. s71359-00-000 04/08 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. these specifications are subject to change without notice. advance information features: ? single voltage read and write operations ? 2.7-3.6v ? serial interface architecture ? nibble-wide multiplexed i/o?s with spi-like serial command structure - mode 0 and mode 3 ? single-bit, spi backwards compatible - read, high-speed read, and jedec id read ? high speed clock frequency ?80 mhz - 300 mbit/s sustained data rate ? burst modes ? continuous linear burst ? 8/16/32/64 byte linear burst with wrap-around ? index jump ? jump to address index within 256 byte page ? jump to address index within 64 kbyte block ? jump to address index to another 64 kbyte block ? superior reliability ? endurance: 100,000 cycles ? greater than 100 years data retention ? low power consumption: ? active read current: 12 ma (typical @ 80 mhz) ? standby current: 8 a (typical) ? fast erase and byte-program: ? chip-erase time: 35 ms (typical) ? sector-/block-erase time: 18 ms (typical) ? page-program ? 256 bytes per page ? fast page program time in 1 ms (typical) ? end-of-write detection ? software polling the busy bit in status register ? flexible erase capability ? uniform 4 kbyte sectors ? four 8 kbyte top parameter overlay blocks ? four 8 kbyte bottom parameter overlay blocks ? two 32 kbyte overlay blocks (one each top and bottom) ? uniform 64 kbyte overlay blocks - sst26vf016 ? 30 blocks - sst26vf032 ? 62 blocks ? write-suspend ? suspend program or erase operation to access another block/sector ? software reset (rst) mode ? software write protection ? block-locking - 64 kbyte blocks, two 32 kbyte blocks, and eight 8 kbyte parameter blocks ? security id ? one-time programmable (otp) 256 bit, secure id - 64 bit unique, factory pre-programmed iden- tifier - 192 bit user-programmable ? temperature range ? commercial: 0c to +70c ? industrial: -40c to +85c ? packages available ? 8-contact wson (6mm x 5mm) ? 8-lead soic (200 mil) ? all non-pb (lead-free) devices are rohs compliant product description the serial quad i/o? (sqi?) family of 4-bit, multiplexed i/o, serial-interface, flash-memory devices features a six- wire, 4-bit i/o interface that allows for low-power, high-per- formance operation in a low pin-count package, occupying less board space and ultimately lowering total system costs. all members of the 26 series, sqi family are manu- factured with sst proprietary, high-performance cmos superflash? technology. the split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. the sst26vf016/032 significantly improve performance and reliability, while lowering power consumption. these devices write (program or erase) with a single power sup- ply of 2.7-3.6v. the total energy consumed is a function of the applied voltage, current, and time of application. since for any given voltage range, the superflash technology uses less current to program and has a shorter erase time, the total energy consumed during any erase or program operation is less than alternative flash memory technolo- gies. sst26vf016/032 are offered in both 8-contact wson (6 mm x 5 mm), and 8-lead soic (200 mil) packages. see figure 2 for pin assignments. serial quad i/o (sqi) flash memory sst26vf016 / sst26vf032 sst25vf016b16mb serial peripheral interface (spi) flash memory
2 advance information serial quad i/o (s qi) flash memory sst26vf016 / sst26vf032 ?2008 silicon storage technology, inc. s71359-00-000 04/08 figure 1: functional block diagram 1359 b1.0 page buffer, i/o buffers and data latches superflash memory x - decoder control logic address buffers and latches ce# y - decoder sck sio [3:0] serial interface
advance information serial quad i/o (sqi) flash memory sst26vf016 / sst26vf032 3 ?2008 silicon storage technology, inc. s71359-00-000 04/08 pin description figure 2: pin description for 8-lead soic and 8-contact wson table 1: pin description symbol pin name functions sck serial clock to provide the timing of the serial interface. commands, addresses, or input data are latc hed on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. sio[3:0] serial data input/output to transfer commands, addresses, or data seri ally into the device or data out of the device. inputs are latched on the rising edge of the serial clock. data is shifted out on the falling edge of the serial clock. the eqio command instructio n sets up these pins for quad i/o mode after a power on reset. si serial data input for spi mode to transfer commands, addresses or data serially into the device. inputs are latched on the rising edge of the serial clock. si is the default state after a power on reset. so serial data output for spi mode to transfer data serially out of the device. data is shifted out on the falling edge of the serial clock. so is the default state after a power on reset. ce# chip enable the device is enabled by a high to lo w transition on ce#. ce# must remain low for the duration of any command sequence; or in t he case of write operations, for the com- mand/data input sequence. v dd power supply to provide power supply voltage: 2.7-3.6v v ss ground t1.0 1359 1 2 3 4 8 7 6 5 ce# so/sio1 sio2 v ss v dd sio3 sck si/sio0 to p v i e w 1359 08-soic s2a p1.0 1 2 3 4 8 7 6 5 ce# so/sio1 sio2 v ss top view v dd sio3 sck si/sio0 1359 08-wson qa p1.0 8- lead soic 8- contact wson
4 advance information serial quad i/o (s qi) flash memory sst26vf016 / sst26vf032 ?2008 silicon storage technology, inc. s71359-00-000 04/08 memory organization the sst26vf016/032 sqi memory array is organized in uniform 4 kbyte erasable sectors with eight 8 kbyte parameters and two 32 kbyte, plus 30/62 64 kbyte, eras- able overlay blocks. figure 3: memory map device operation the sst26vf016/032 supports both serial peripheral interface (spi) bus protocol and the new 4-bit multiplexed serial quad i/o (sqi) bus protocol. to provide backward compatibility to trad itional spi serial flash devices, the device?s initial state after a power-on reset is spi bus proto- col supporting only read, high speed read, and jedec- id read instructions. a command instruction configures the device to serial quad i/o bus protocol. the dataflow in this bus protocol is controlled with four multiplexed i/o sig- nals, a chip enable (ce#), and serial clock (sck). this sqi flash memory supports both mode 0 (0,0) and mode 3 (1,1) bus operations. the difference between the two modes, as shown in figures 4 and 5, is the state of the sck signal when the bus master is in stand-by mode and no data is being transferred. the sck signal is low for mode 0 and sck signal is high for mode 3. for both modes, the serial data i/o (sio[3:0]) is sampled at the ris- ing edge of the sck clock signal for input, and driven after the falling edge of the sck clock signal for output. the tra- ditional spi protocol uses s eparate input (si) and output (so) data signals as shown in figure 4. the sst26vf016/ 032 use four multiplexed signals, sio[3:0], for both data in and data out, as shown in figure 5. this quadruples the traditional bus transfer speed at the same clock frequency, without the need for more pins on the package. 1359 f41.0 top of memory block 8 kbyte 8 kbyte 8 kbyte 8 kbyte 32 kbyte 64 kbyte 64 kbyte 64 kbyte 32 kbyte 8 kbyte 8 kbyte 8 kbyte 8 kbyte bottom of memory block 4 kbyte 4 kbyte 4 kbyte 4 kbyte . . . 2 sectors for 8 kbyte blocks 8 sectors for 32 kbyte blocks 16 sectors for 64 kbyte blocks . . .
advance information serial quad i/o (sqi) flash memory sst26vf016 / sst26vf032 5 ?2008 silicon storage technology, inc. s71359-00-000 04/08 figure 4: spi protocol (traditional 25 serial spi device) figure 5: sqi quad i/o protocol 1359 f03.0 mode 3 sck si so ce# mode 3 don't care bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mode 0 mode 0 high impedance msb msb 1359 f04.2 mode 3 clk sio(3:0) ce# mode 3 c1 c0 a5 a4 a3 a2 a1 a0 x x h0 l0 h1 l1 h2 l2 h3 l3 mode 0 mode 0 msb x = don?t care or high impediance
6 advance information serial quad i/o (s qi) flash memory sst26vf016 / sst26vf032 ?2008 silicon storage technology, inc. s71359-00-000 04/08 device protection the sst26vf016/032 have a block-protection register which provides a software mechanism to write-lock the array and write-lock, and/or read-lock, the parameter blocks. the block-protection register is 48/80 bits wide per device: two bits each for the eight 8 kbyte parameter blocks (write-lock and read-lock), and one bit each for the remaining 32 kbyte and 64 kbyte overlay blocks (write- lock). see tables 8 - 9 for address range protected per reg- ister bit. each bit in the block-protection register can be written to a ?1? (protected) or ?0? (unprotected). for the parameter blocks, the most significant bit is for read-lock, and the least significant bit is for write-lock. read-locking the parameter blocks provides additional secu rity for sensitive data after retrieval (e.g., after initial boot). if a block is read-locked all reads to the block return data 00h. all blocks are write- locked and read-unlocked after power-up or reset. the write block locking register command is a two cycle com- mand requiring write-enable (wren) to be executed prior to the write block-protection register command. figure 6: block locking memory map 1359 f40.2 top of memory block 8 kbyte 8 kbyte 8 kbyte 8 kbyte 32 kbyte 64 kbyte 64 kbyte 64 kbyte 32 kbyte 8 kbyte 8 kbyte 8 kbyte 8 kbyte read lock write lock read lock write lock write lock bottom of memory block . . .
advance information serial quad i/o (sqi) flash memory sst26vf016 / sst26vf032 7 ?2008 silicon storage technology, inc. s71359-00-000 04/08 write-protection lock-down to prevent changes, the block-protection register can be set to write-protection lock-down using the lock down block protection register (lpbr) command. once the write-protection lock-down is enabled, the block-protec- tion register can not be changed. to avoid inadvertent lock down, the wren command must be executed prior to the lbpr command. to reset write-protection lock-down, power cycle the device. the protection status may be read from the status register. security id sst26vf016/032 offer a 256-bit security id (sec id) fea- ture. the security id space is divided into two parts ? one factory-programmed, 64-bit segment and one user-pro- grammable 192-bit segment. the factory-programmed segment is programmed at sst with a unique number and cannot be changed. the user-programmable segment is left unprogrammed for the customer to program as desired. use the secid program command to program the security id using the address shown in table 7. once programmed, the security id can be locked using the lockout sec id command. this prevents any future write to the security id. the factory-programmed portion of the security id can never be programmed, and none of the security id can be erased.
8 advance information serial quad i/o (s qi) flash memory sst26vf016 / sst26vf032 ?2008 silicon storage technology, inc. s71359-00-000 04/08 status register the status register is a read-only register that provides sta- tus on whether the flash memory array is available for any read or write operation, whether the device is write enabled, and whether an erase or program operation is suspended. during an internal erase or program opera- tion, the status register may be read to determine the com- pletion of an operation in progress. table 2 describes the function of each bit in the status register. table 2: status register bit name function default at power-up 0 res reserved for future use 0 1 wel write-enable latch status 1 = device is memory write enabled 0 = device is not memory write enabled 0 2 wse write suspend-erase status 1 = erase suspended 0 = erase is not suspended 0 3 wsp write suspend-program status 1 = program suspended 0 = program is not suspended 0 4 wpld write protection lock-down status 1 = write protection lock-down enabled 0 = write protection lock-down disabled 0 5 sec 1 1. the security id status will always be ?1? at power-up after a successful execution of the lockout sec id instruction. security id status 1 = security id space locked 0 = security id space not locked 0 6 res reserved for future use 0 7 busy write operation status 1 = internal write operation is in progress 0 = no internal write operation is in progress 0 t2.0 1359
advance information serial quad i/o (sqi) flash memory sst26vf016 / sst26vf032 9 ?2008 silicon storage technology, inc. s71359-00-000 04/08 write-enable latch (wel) the write-enable-latch (wel) bit indicates the status of the internal memory?s write-enable latch. if the wel bit is set to ?1?, the device is write enabled. if the bit is set to ?0? (reset), the device is not write-enabled and does not accept any memory program or erase, protection register write, or lock-down commands. the write-enable-latch bit is automatically reset under the following conditions: ? power-up ? reset ? write-disable (wrdi) instruction completion ? page-program instruction completion ? sector-erase instruction completion ? block-erase instruction completion ? chip-erase instruction completion ? write-block-protection register instruction ? lock-down block-protection register instruction ? program security id instruction completion ? lockout security id instruction completion ? write-suspend instruction write suspend-erase status (wse) the write suspend-erase status (wse) indicates when an erase operation has been suspended. the wse bit is ?1? after the host issues a suspend command during an erase operation. once the suspended erase resumes, the wse bit is reset to ?0.? write suspend-program status (wsp) the write suspend-program status (wsp) bit indicates when a program operation has been suspended. the wsp is ?1? after the host issues a suspend command dur- ing the program operation. once the suspended program resumes, the wsp bit is reset to ?0.? write protection-lockdown status (wpld) the write protection-lockdown status (wpld) bit indi- cates when the block protection register is locked-down to prevent changes to the protection settings. the wpld is ?1? after the host issues a lock-down block protection com- mand. after a power cycle, the wpld bit is reset to ?0.? security id status (sec) the security id status (sec) bit indicates when the secu- rity id space is locked to prevent a write command. the sec is ?1? after the host issues a lockout sid command. once the host issues a lockout sid command, the sec bit can never be reset to ?0.? busy the busy bit determines whether there is an internal erase or program operation in progress. if the busy bit is ?1?, the device is busy with an internal erase or program operation. if the bit is ?0?, no erase or program operation is in progress.
10 advance information serial quad i/o (s qi) flash memory sst26vf016 / sst26vf032 ?2008 silicon storage technology, inc. s71359-00-000 04/08 instructions instructions are used to read, write (erase and program), and configure the sst26vf016/032. the instruction bus cycles are eight bits each for commands (op code), data, and addresses. prior to executing any write instructions, the write-enable (wren) instruction must be executed. the complete list of the instructions is provided in table 3. all instructions are synchronized off a high to low transition of ce#. inputs are accepted on the rising edge of sck starting with the most significant bit. ce# must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been input (except for read instructions). any low-to-high transition on ce# before receiving the last nibble of an instruction bus cycle, will terminate the instruction in being entered and return the device to the standby mode. table 3: device operation instructions for sst26vf016/032 instruction description command cycle 1 1. one bus cycle is two clock peri ods (command, access, or data). address cycle(s) 2 2. address bits above the most signi ficant bit of each density can be v il or v ih. dummy cycle(s) data cycle(s) maximum frequency nop no operation 00h 0 0 0 80 mhz rsten reset enable 66h 0 0 0 rst 3 3. rst command only executed if rsten command is execut ed first. any intervening command will disable reset. reset memory 99h 0 0 0 eqio enable quad i/o 38h 0 0 0 rstqio 4 4. device accepts eight-clocks command in spi mode, or two-clocks command in sqi mode. reset quad i/o ffh 0 0 0 read 5 read memory 03h 3 0 1 to 33 mhz high-speed read 5 read memory at higher speed 0bh 3 1 1 to 80 mhz set burst 6 set burst length c0h 0 0 1 read burst nb burst with wrap 0ch 3 1 n to read pi 7 jump to address within 256 byte page indexed by n 08h 1 1 1 to read i jump to address within block indexed by n 09h 2 2 1 to read bi jump to block indexed by n 10h 1 2 1 to jedec-id 5,8 jedec-id read 9fh 0 0 3 to quad j-id 8 quad i/o j-id read afh 0 0 3 to sector erase 9 erase 4 kbytes of memory array 20h 3 0 0 block erase 10 erase 64, 32 or 8 kbytes of memory array d8h 3 0 0 chip erase erase full array c7h 0 0 0 page program program 1 to 256 data bytes 02h 3 0 1 to 256 write suspend suspends program/erase b0h 0 0 0 write resume resumes program/erase 30h 0 0 0 read sid read security id 88h 1 1 1 to 32 program sid 11 program user security id area a5h 1 0 1 to 24 lockout sid 11 lockout security id programming 85h 0 0 0 rdsr 12 read status register 05h 0 0 1 to wren write enable 06h 0 0 0 wrdi write disable 04h 0 0 0 rbpr 13 read block protection register 72h 0 0 1 to m/4 wbpr 11,13 write block protection register 42h 0 0 1 to m/4 lbpr 11 lock down block protection register 8dh 0 0 0 t3.0 1359
advance information serial quad i/o (sqi) flash memory sst26vf016 / sst26vf032 11 ?2008 silicon storage technology, inc. s71359-00-000 04/08 no operation (nop) the no operation command only cancels a reset enable command. nop has no impact on any other command. reset-enable (rsten ) and reset (rst) the reset operation is used as a system (software) reset that puts the device in normal operating ready mode. this operation consists of two commands: reset-enable (rsten) and reset (rst). to reset the sst26vf016/032 the host drives ce# low, sends the reset-enable command (66h), and drives ce# high. next, the host drives ce# low again, sends the reset command (99h), and drives ce# high. the reset operation requires the reset-enable command followed by the reset command. any command other than the reset command after the reset-enable command will disable the reset-enable. a successful command executi on will reset the status reg- ister to data = 00h, the block-protection register to write- locked/read-unlocked, and the burst length to 8 bytes, which are their respective def ault states, see figure 7. a device reset during an active program or erase operation aborts the operation, which can cause the data of the tar- geted address range to be corrupted or lost. depending on the prior operation, the reset timing may vary. recovery from a write operation requires more latency time than recovery from other operations. figure 7: reset sequence 5. after a power cycle, read, high-speed read, and jedec-id re ad instructions input and output cycles are spi bus protocol. 6. burst length? n = 8 bytes: data(00h); n = 16 bytes: data (01h); n = 32 bytes: data(02h); n = 64 bytes: data(03h). 7. address is 256 bytes page align (2?s complement) 8. the quad j-id read wraps the three quad j-id bytes of data until terminated by a low-to-high transition on ce# 9. sector addresses: use a ms - a 12 , remaining address are don?t care, but must be set to v il or v ih . 10. blocks are 64 kbyte, 32 kbyte, or 8kbyte, depending on location. block erase address: a ms - a 16 for 64 kbyte; a ms - a 15 for 32 kbyte; a ms - a 13 for 8 kbyte. remaining addresses are don?t care, but must be set to v il or v ih . 11. requires a prior wren command. 12. the read-status register is continuous with ongoing clock cycles until terminated by a low-to-high transition on ce#. 13. data is written/read from msb to ls b. msb = 48 for sst26vf016; 80 for sst26vf032 1359 f05.0 mode 3 clk sio(3:0) ce# mode 3 c1 c3 c2 c0 mode 0 mode 3 mode 0 mode 0 t ceh note: c[1:0] = 66h; c[3:2] = 99h
12 advance information serial quad i/o (s qi) flash memory sst26vf016 / sst26vf032 ?2008 silicon storage technology, inc. s71359-00-000 04/08 read (33 mhz) the read instruction, 03h, is supported in spi bus proto- col only with clock frequencies up to 33 mhz. this com- mand is not supported in sqi bus protocol. the device outputs the data starting from the specified address loca- tion, then continuously streams the data output through all addresses until terminated by a low-to-high transition on ce#. the internal address po inter will automatically incre- ment until the highest memory address is reached. once the highest memory address is reached, the address pointer will automatically retu rn to the beginning (wrap- around) of the address space. initiate the read instruction by executing an 8-bit com- mand, 03h, followed by address bits a23:a0. ce# must remain active low for the duration of the read cycle. sio2 and sio3 must be driven v ih for the duration of the read cycle. see figure 8 for read sequence. figure 8: read sequence (spi) enable quad i/o (eqio) the enable quad i/o (eqio) instruction, 38h, enables the flash device for sqi bus operation. upon completion of the instruction, all in structions thereafte r will be 4-bit multi- plexed input/output until a power cycle or a ?reset quad i/ o instruction? instruction. see figure 9. figure 9: enable quad i/o sequence reset quad i/o (rstqio) the reset quad i/o instruction, ffh, resets the device to 1-bit spi protocol operation. to execute a reset quad i/o operation, the host drives ce# low, sends the reset quad i/o command cycle (ffh) then, drives ce# high. the de- vice accepts either spi (8 clocks) or sqi (2 clocks) com- mand cycles. for spi, sio[3:1] are don?t care for this command, but should be driven to v ih or v il . 1359 f29.0 ce# so si sck add. 012345678 add. add. 03 high impedance 15 16 23 24 31 32 39 40 70 47 48 55 56 63 64 n+2 n+3 n+4 n n+1 d out msb msb msb mode 0 mode 3 d out d out d out d out note: sio2 and sio3 must be driven v ih 1359 f43.0 mode 3 0 1 sck sio0 ce# mode 0 234567 38 sio[3:1] note: c[1:0] = 38h
advance information serial quad i/o (sqi) flash memory sst26vf016 / sst26vf032 13 ?2008 silicon storage technology, inc. s71359-00-000 04/08 high-speed read (80 mhz) the high-speed read instruction, 0bh, is supported in both spi bus protocol and sqi protocol. on power-up, the device is set to use spi. initiate high-speed read by executing an 8-bit command, 0bh, followed by address bits [a23-a0] and a dummy byte. ce# must remain active low for the duration of the high- speed read cycle. sio2 and sio3 must be driven v ih for the duration of the read cycle. see figure 10 for the high- speed read sequence for spi bus protocol. figure 10: high-speed read sequence (spi) to use sqi protocol, the host drives ce# low then send the read command cycle command, 0bh, followed by three address cycles and one dummy cycle. each cycle is two nibbles (clocks) long, most significant nibble first. after the dummy cycle, the serial quad i/o (sqi) flash memory outputs data on the falling edge of the sck signal starting from the specified address location. the device continually streams data output through all addresses until terminated by a low-to-high transition on ce#. the internal address pointer automatically increments until the highest memory address is reached, at which point the address pointer returns to the beginning of the address space. during this operation, blocks that are read-locked will out- put data 00h. figure 11: high-speed read sequence (sqi) 1359 f31.0 ce# so/sio1 si/sio0 sck add. 012345678 add. add. 0b high impedance 15 16 23 24 31 32 39 40 47 48 55 56 63 64 n+2 n+3 n+4 n n+1 x msb mode 0 mode 3 d out d out d out d out 80 71 72 d out note: sio2 and sio3 must be driven v ih 1359 f06.2 mode 3 0 1 2 9 16 clk sio(3:0) ce# mode 3 c1 c0 a5 a4 a3 a2 a1 a0 x x h0 l0 h1 l1 h2 l2 h3 l3 mode 0 mode 0 msb data out data in note: c[1:0] = 0bh
14 advance information serial quad i/o (s qi) flash memory sst26vf016 / sst26vf032 ?2008 silicon storage technology, inc. s71359-00-000 04/08 set burst the set burst command specifies the number of bytes to be output during a read burst command before the device wraps around. to set the burst length the host drives ce# low, sends the set burst command cycle (c0h) and one data cycle, then drives ce# high. a cycle is two nibbles, or two clocks, long, most significant nibble first. after power-up or reset, the burst length is set to eight bytes (00h). see table 4 for burst length data and figure 12 for the sequence. figure 12: set burst length sequence read burst to execute a read burst operation the host drives ce# low, then sends the read burst command cycle (0ch), fol- lowed by three address cycles, and then one dummy cycle. each cycle is two nibbles (clocks) long, most significant nib- ble first. after the dummy cycle, the device outputs data on the fall- ing edge of the sck signal starting from the specified address location. the data output stream is continuous through all addresses until terminated by a low-to-high tran- sition on ce#. during read burst, the internal address pointer automati- cally increments until the last byte of the burst is reached, then jumps to first byte of the burst. all bursts are aligned to addresses within the burst length, see table 5. for exam- ple, if the burst length is eight bytes, and the start address is 06h, the burst sequence would be: 06h, 07h, 00h, 01h, 02h, 03h, 04h, 05h, 06h, etc. the pattern would repeat until the command was terminated by a low-to-high transition on ce#. during this operation, blocks that are read-locked will out- put data 00h. index jump index jump allows the host to read data using relative addressing instead of absolute addressing; in some cases this reduces the number of input clocks required to access data. the sst26vf016/032 support three index jump options: ? read page-index-jump to address index within 256 byte page ? read index-jump to address index within 64 kbyte block ? read block-index - jump to address index in another 64 kbyte block. index jumps following a burst read command are refer- enced from the last input address. for example, the device initiates a 64-byte read burst instruction from address location 1eh and outputs an arbitrary number of bytes. when the device issues a read page-index instruction with 40h as the offset, the device will output data from address location 5eh. index jump operations following a high speed read (continuous read) instruction are refer- enced from the last address from which the full byte of data was output. data output by any of the index-jump commands follows the pattern of the last non-index-jump command. for example, a read page-index command following a read burst, with 64-byte wrap length, will continue to deliver data that wraps at 64-byte boundaries after jumping to the address specified in the read page-index command. table 4: burst length data burst length high nibble (h0) low nibble (l0) 8 bytes 0h 0h 16 bytes 0h 1h 32 bytes 0h 2h 64 bytes 0h 3h t4.0 1359 1359 f32.0 mode 3 0 1 sck sio(3:0) ce# c1 c0 mode 0 23 h0 l0 msn lsn note: msn = most significant nibble, lsn = least significant nibble table 5: burst address ranges burst length burst address ranges 8 bytes 00-07h, 08-0fh, 10-17h, 18-1fh... 16 bytes 00-0fh, 10-1fh, 20-2fh, 30-3fh... 32 bytes 00-1fh, 20-2fh, 30-3fh, 40-4fh... 64 bytes 00-3fh, 40-7fh, 80-bfh, c0-ffh t5.0 1359
advance information serial quad i/o (sqi) flash memory sst26vf016 / sst26vf032 15 ?2008 silicon storage technology, inc. s71359-00-000 04/08 read page-index (read pi) the read page-index (read pi) instruction increments the address counter within a page of 256 bytes. to execute a read pi operation the host drives ce# low then sends the read pi command cycle (08h), one address cycle, and one dummy cycle. each cycle is two nibbles (clocks) long, most significant nibble first. the address cycle contain a two?s complement number that specifies the number of bytes and direction the address pointer will jump. for example, to jump ahead 127 bytes a1:a0 = 7fh; to jump back 127 bytes a1:a0 = 81h. the read pi command does not cross 256 bytes page boundaries. if the jump distance exceeds the 256 bytes boundary, the address pointer wraps around to the begin- ning of the page, if the jump is forward, or to the end of the page, if the jump is backward. after the dummy cycle, the device outputs data on the falling edge of the sck signal starting from the specified address location. read index the read index (read i) instruction increments the address counter a specified number of bytes within a 64 kbyte block. to execute a read i operation the host drives ce# low then sends the read i command cycle (09h), two address cycles, and two dummy cycles. each cycle is two nibbles (clocks) long, most significant nibble first. the address cycles contain a two?s complement number that specifies the number of bytes and direction the address pointer will jump. for example, to jump ahead 256 bytes, the address cycles would be 0100h; to jump back 256 bytes, the address cycles would be ff00h. the read i command can not cross 64 kbyte block bound- aries, but it can cross boundaries of smaller blocks. if the jump distance exceeds the 64 kbyte block boundary, the address pointer wraps around to the beginning of the block, if the jump is forward, and to the end of the block, if the jump is backward. after the dummy cycles, the device out- puts data on the falling edge of the sck signal starting from the specified address location. read block index (read bi) the read block index (read bi) instruction increments the address counter a specified number of 64 kbyte blocks. to execute a read bi operation the host drives ce# low, then sends the read bi command cycle (10h), one address cycle, and two dummy cycles. each cycle is two nibbles (clocks) long, most significant nibble first. the address cycle contains a two?s complement number specifying the number of bl ocks and the direction the address pointer will jump. the least significant address bits, a15:a0, do not change. after the dummy cycle, the device outputs data on the fall- ing edge of the sck signal starting from the specified address location.
16 advance information serial quad i/o (s qi) flash memory sst26vf016 / sst26vf032 ?2008 silicon storage technology, inc. s71359-00-000 04/08 jedec-id read (spi protocol) using traditional spi protocol , the jedec-id read instruc- tion identifies the device as sst26vf016/032 and the manufacturer as sst. to execute a jecec-id operation the host drives ce# low then sends the jedec-id com- mand cycle (9fh). for spi modes, each cycle is eight bits (clocks) long, most significant bit first. immediately following the command cycle the device out- puts data on the falling edge of the sck signal. the data output stream is continuous until terminated by a low-to- high transition on ce#. the device outputs three bytes of data: manufacturer, device type, and device id, see table 6. see figure 13 for instruction sequence. figure 13: jedec-id sequence (spi mode) quad j-id read (sqi protocol) the quad j-id read instruction identifies the devices as sst26vf016/032 and manufacturer as sst. to execute a quad j-id operation the host drives ce# low and then sends the quad j-id command cycle (afh). each cycle is two nibbles (clocks) long, most significant nibble first. immediately following the command cycle the device out- puts data on the falling edge of the sck signal. the data output stream is continuous until terminated by a low-to- high transition of ce#. the device outputs three bytes of data: manufacturer, device type, and device id, see table 6. see figure 14 for instruction sequence. figure 14: quad j-id read sequence table 6: device id data output product manufacturer id (byte 1) device id device type (byte 2) device id (byte 3) sst26vf016 bfh 26h 01h sst26vf032 bfh 26h 02h t6.1 1359 26 device id 1359 f38.0 ce# so si sck 012345678 high impedance 15 16 14 28 29 30 31 bf mode 3 mode 0 msb msb 9 10111213 1718 32 34 9f 19 20 21 22 23 33 24 25 26 27 note: sio2 and sio3 must be driven v ih 1359 f39.0 mode 3 0 sck sio(3:0) ce# c1 c0 mode 0 2 h0 l0 msn lsn 4 h1 l1 6 h2 l2 8 h0 l0 10 h1 l4 12 h2 l2 n hn ln bfh n 26h device id bfh 26h device id note: msn = most significant nibble; lsn= least significant nibble c[1:0]=afh
advance information serial quad i/o (sqi) flash memory sst26vf016 / sst26vf032 17 ?2008 silicon storage technology, inc. s71359-00-000 04/08 sector-erase the sector-erase instruction cl ears all bits in the selected 4 kbyte sector to ?1,? but it does not change a protected memory area. prior to any write operation, the write- enable (wren) instruction must be executed. to execute a sector-erase operation, the host drives ce# low, then sends the sector erase command cycle (20h) and three address cycles, and then drives ce# high. each cycle is two nibbles, or clocks, long, most significant nibble first. address bits [a ms :a 12 ] (a ms = most significant address) determine the sector address (sax); the remain- ing address bits can be v il or v ih . poll the busy bit in the status register or wait t se for the completion of the internal, self-timed, sector-erase operat i on. see figure 15 for the sector-erase sequence. figure 15: 4 kbyte sector-erase sequence block-erase the block-erase instruction clears all bits in the selected block to ?1?. block sizes can be 8 kbyte, 32 kbyte or 64 kbyte depending on address, see figure 5, memory map, for details. a block-erase instruction applied to a protected memory area will be ignored. prior to any write operation, execute the wren instruction. keep ce# active low for the duration of any command sequence. to execute a block-erase ope ration, the host drives ce# low then sends the block-erase command cycle (d8h), three address cycles, then drives ce# high. each cycle is two nibbles, or clocks, long, most significant nibble first. address bits a ms -a 13 determine the block address; the remaining address bits can be v il or v ih . for 32 kbyte blocks, a 14 :a 13 can be v il or v ih ; for 64 kbyte blocks, a 15 :a 13 can be v il or v ih . poll the busy bit in the status register or wait t be for the completion of the internal, self- timed, block-erase operat i on see figure 16 for the block- erase sequence. figure 16: block-erase sequence 1359 f07.0 mode 3 0 1 sck sio(3:0) ce# c1 c0 mode 0 2 a5 a4 msn lsn 4 a3 a2 6 a1 a0 note: msn = most significant nibble, lsn = least significant nibble c[1:0] = 20h 1359 f08.0 mode 3 0 1 sck sio(3:0) ce# c1 c0 mode 0 2 a5 a4 msn lsn 4 a3 a2 6 a1 a0 note: msn = most significant nibble, lsn = least significant nibble c[1:0] = d8h
18 advance information serial quad i/o (s qi) flash memory sst26vf016 / sst26vf032 ?2008 silicon storage technology, inc. s71359-00-000 04/08 chip-erase the chip-erase instruct ion clears all bits in the device to ?1.? the chip-erase instruction is ignored if any of the memory area is protected. prior to any write operation, execute the the wren instruction. to execute a chip-erase operation, the host drives ce# low, sends the chip-erase command cycle (c7h), then drives ce# high. a cycle is two nibbles, or clocks, long, most significant nibble first. poll the busy bit in the status register or wait t ce for the completion of the internal, self- timed, chip-erase operat i on. see figure 17 for the chip erase sequence. figure 17: chip-erase sequence page-program the page-program instruction programs up to 256 bytes of data in the memory. the selected page address must be in the erased state (ffh) before initiating the page-program operation. a page-program applied to a protected memory area will be ignored. prior to the program operation, exe- cute the wren instruction. to execute a page-program operation, the host drives ce# low then sends the page program command cycle (02h), three address cycles followed by the data to be pro- grammed, then drives ce# high. the programmed data must be between 1 to 256 bytes and in whole byte incre- ments; sending an odd number of nibbles will cause the last nibble to be ignored. each cycle is two nibbles (clocks) long, most significant bit first. poll the busy bit in the sta- tus register or wait t pp for the completion of the internal, self-timed, page-program operat i on. see figure 18 for the page-program sequence. when executing page-program, the memory range for the sst26vf016/032 is divided into 256 byte page bound- aries. the device handles shifting of more than 256 bytes of data by maintaining the last 256 bytes of data as the cor- rect data to be programmed. if the target address for the page-program instruction is not the beginning of the page boundary (a7:a0 are not all zero), and the number of data input exceeds or overlaps the end of the address of the page boundary, the excess data inputs wrap around and will be programmed at the start of that target page. figure 18: page-program sequence 1359 f09.0 mode 3 0 1 sck sio(3:0) ce# c1 c0 mode 0 note: c[1:0] = c7h 1359 f10.0 mode 3 0 sck sio(3:0) ce# c1 c0 mode 0 2 a5 a4 msn lsn 4 a3 a2 6 a1 a0 8 h0 l0 10 h1 l1 12 h2 l2 542 hn ln data byte 0 data byte 1 data byte 2 data byte 255 note: msn = most significant nibble, lsn = least significant nibble c[1:0] = 02h
advance information serial quad i/o (sqi) flash memory sst26vf016 / sst26vf032 19 ?2008 silicon storage technology, inc. s71359-00-000 04/08 write-suspend and write-resume write-suspend allows the interruption of sector-erase, block-erase or page-program operations in order to erase, program, or read data in another portion of memory. the original operation can be continued with the write-resume command. only one write operation can be suspended at a time; if an operation is already suspended, the device will ignore the write-suspend command. write-suspend during chip- erase is ignored; chip-erase is not a valid command while a write is suspended. write-suspend during sector-erase or block-erase issuing a write-suspend instruction during sector-erase or block-erase allows the host to program or read any sector that was not being erased. the device will ignore any pro- gramming commands pointing to the suspended sector(s). any attempt to read from the suspended sector(s) will out- put unknown data because the sector- or block-erase will be incomplete. to execute a write-suspend operation, the host drives ce# low, sends the write suspend command cycle (b0h), then drives ce# high. a cycle is two nibbles long, most sig- nificant nibble first. the status register indicates that the erase has been suspended by changing the wse bit from ?0? to ?1,? but the device will not accept another command until it is ready. to determine when the device will accept a new command, poll the busy bit in the status register or wait t ws . write suspend during page programming issuing a write-suspend instruction during page program- ming allows the host to erase or read any sector that is not being programmed. erase commands pointing to the sus- pended sector(s) will be ignored. any attempt to read from the suspended page will output unknown data because the program will be incomplete. to execute a write suspend operation, the host drives ce# low, sends the write suspend command cycle (b0h), then drives ce# high. a cycle is two nibbles long, most signifi- cant nibble first. the status register indicates that the pro- gramming has been suspended by changing the wsp bit from ?0? to ?1,? but the devi ce will not accept another com- mand until it is ready. to determine when the device will accept a new command, poll the busy bit in the status register or wait t ws . write-resume write-resume restarts a write command that was sus- pended, and changes the suspend status bit in the status register (wse or wsp) back to ?0?. to execute a write-resume operation, the host drives ce# low, sends the write resume command cycle (30h), then drives ce# high. a cycle is two nibbles long, most signifi- cant nibble first. to determine if the internal, self-timed write operation completed, poll the busy bit in the status register, or wait the specified time t se , t be or t pp for sec- tor-erase, block-erase, or page-programming, respec- tively. the total write time before suspend and after resume will not exceed the uninterrupted write times t se , t be or t pp .
20 advance information serial quad i/o (s qi) flash memory sst26vf016 / sst26vf032 ?2008 silicon storage technology, inc. s71359-00-000 04/08 read security id to execute a read security id (sid) operation, the host drives ce# low, sends the read security id command cycle (88h), one address cycle, and then one dummy cycle. each cycle is two nibbles long, most significant nib- ble first. after the dummy cycle, the device outputs data on the fall- ing edge of the sck signal, starting from the specified address location. the data output stream is continuous through all sid addresses until terminated by a low-to-high transition on ce#. the internal address pointer automati- cally increments until the last sid address is reached, then outputs 00h until ce# goes high. program security id the program security id instruction programs one to 24 bytes of data in the user-programmable, security id space. the device ignores a program security id instruction point- ing to an invalid or protected address, see table 7. prior to the program operation, execute wren. to execute a program sid operation, the host drives ce# low, sends the program security id command cycle (a5h), one address cycle, the data to be programmed, then drives ce# high. the programmed data must be between 1 to 24 bytes and in whole byte increments; sending an odd num- ber of nibbles will cause the la st nibble to be ignored. each cycle is two nibbles long, most significant nibble first. to determine the completion of the internal, self-timed pro- gram sid operation, poll the busy bit in the software sta- tus register, or wait t psid for the completion of the internal self-timed program security id operation. lockout security id the lockout security id instruction prevents any future changes to the security id. to execute a lockout sid, the host drives ce# low, sends the lockout security id com- mand cycle (85h), then drives ce# high. a cycle is two nib- bles long, most significant nibble first. the user map polls the busy bit in the software status register or waits t psid for the completion of he lockout security id operation. table 7: program security id program security id address range pre-programmed at factory 00h ? 07h user programmable 08h ? 1fh t7.0 1359
advance information serial quad i/o (sqi) flash memory sst26vf016 / sst26vf032 21 ?2008 silicon storage technology, inc. s71359-00-000 04/08 read-status register (rdsr) the read-status register (rdsr) command outputs the contents of the status register. the status register may be read at any time even during a write operation. when a write is in progress, check the busy bit before sending any new commands to assure that the new commands are properly received by the device. to execute a read-status-register operation the host drives ce# low, then sends the read-status-register com- mand cycle (05h). each cycle is two nibbles long, most sig- nificant nibble first. immediately after the command cycle, the device outputs data on the falling edge of the sck sig- nal. the data output stream continues until terminated by a low-to-high transition on ce#. see figure 19 for the rdsr instruction sequence. figure 19: read-status-register (rdsr) sequence write-enable (wren) the write enable (wren) instruction sets the write- enable-latch bit in the status register to ?1,? allowing write operations to occur. the wren instruction must be exe- cuted prior to any of the following operations: sector erase, block erase, chip erase, page program, program security id, lockout security id, write block-protection register and lockdown block-protection register. to execute a write enable the host drives ce# low then sends the write enable command cycle (06h) then drives ce# high. a cycle is two nibbles (clocks) long, most significant nibble first. see figure 20 for the wren instruction sequence. figure 20: write-enable sequence write-disable (wrdi) the write-disable (wrdi) instruction sets the write- enable latch bit in the status register to ?0,? preventing write execution without a prior wren instruction. to exe- cute a write-disable, the host drives ce# low, sends the write enable command cycle (04h), then drives ce# high. a cycle is two nibbles long, most significant nibble first. figure 21: write-disable (wrdi) sequence 1359 f11.0 mode 3 0 sck sio(3:0) ce# c1 c0 mode 0 2 h0 l0 msn lsn 4 h0 l0 6 h0 l0 8n h1 l1 status byte status byte status byte status byte note: msn = most significant nibble ; lsn = least significant nibble c[1:0] = 05h 1359 f12.0 mode 3 0 1 sck sio(3:0) ce# c1 c0 mode 0 note: c[1:0] = 06h 1359 f33.0 mode 3 0 1 sck sio(3:0) ce# c1 c0 mode 0 note: c[1:0] = 04h
22 advance information serial quad i/o (s qi) flash memory sst26vf016 / sst26vf032 ?2008 silicon storage technology, inc. s71359-00-000 04/08 read block-protecti on register (rbpr) the read block-protection register instruction outputs the block-protection register data which determines the pro- tection status. to execute a read block-protection register operation. the host drives ce# low, and then sends the read block-protection register command cycle (72h). each cycle is two nibbles long, most significant nibble first. after the command cycle, the device outputs data on the falling edge of the sck signal starting with the most signifi- cant nibble, see tables 8 - 9 for definitions of each bit in the block-protection register. the rbpr command does not wrap around. after all data has been output, the device with output 0h until terminated by a low-to-high transition on ce#. see figure 22. figure 22: read block protection register sequence write block-protecti on register (wbpr) to execute a write block-protection register operation the host drives ce# low; sends the program security id com- mand cycle (42h); then sends one to six cycles of data for sst25vf016, or one to 10 cycles of data for sst25vf032, and finally drives ce# high. each cycle is two nibbles long, most significant nibble first. if the host sends less data than the length of the register, the remain- ing bytes will not be changed. sending an odd number of data nibbles is allowed. see tables 8 - 9 for definitions of each bit in the block-protection register. figure 23: write block protection register sequence 1359 f34.2 mode 3 0 sck sio(3:0) ce# c1 c0 2 h0 l0 msn lsn 4 h1 l1 6 h2 l2 8 h3 l3 10 h4 l4 12 h5 l5 n hn l bpr [m:m-7] bpr [7:0] note: msn = most significant nibble, lsn = least significant nibble block protection register (bpr) m = 48/80 for sst26vf016/sst26vf032 respectively c[1:0]=72h 1359 f35.1 mode 3 0 sck sio(3:0) ce# c1 c0 mode 0 2 h0 l0 msn lsn 4 h1 l1 6 h2 l2 8 h3 l3 10 h4 l4 12 h5 l5 n hn ln bpr [m:m-7] bpr [7:0] note: msn = most significant nibble, lsn = least significant nibble block protection register (bpr) m = 48/80 for sst26vf016/sst26vf032 respectively c[1:0]=42h
advance information serial quad i/o (sqi) flash memory sst26vf016 / sst26vf032 23 ?2008 silicon storage technology, inc. s71359-00-000 04/08 table 8: block-protection register for 26vf016 bpr bits address range protected block size read lock write lock 47 46 1fe000h - 1fffffh 8 kbyte 45 44 1fc000h - 1fdfffh 8 kbyte 43 42 1fa000h - 1fbfffh 8 kbyte 41 40 1f8000h - 1f9fffh 8 kbyte 39 38 006000h - 007fffh 8 kbyte 37 36 004000h - 005fffh 8 kbyte 35 34 002000h - 003fffh 8 kbyte 33 32 000000h - 001fffh 8 kbyte 31 1f0000h - 1f7fffh 32 kbyte 30 008000h - 00ffffh 32 kbyte 29 1e0000h - 1effffh 64 kbyte 28 1d0000h - 1dffffh 64 kbyte 27 1c0000h - 1cffffh 64 kbyte 26 1b0000h - 1bffffh 64 kbyte 25 1a0000h - 1affffh 64 kbyte 24 190000h - 19ffffh 64 kbyte 23 180000h - 18ffffh 64 kbyte 22 170000h - 17ffffh 64 kbyte 21 160000h - 16ffffh 64 kbyte 20 150000h - 15ffffh 64 kbyte 19 140000h - 14ffffh 64 kbyte 18 130000h - 13ffffh 64 kbyte 17 120000h - 12ffffh 64 kbyte 16 110000h - 11ffffh 64 kbyte 15 100000h - 10ffffh 64 kbyte 14 0f0000h - 0fffffh 64 kbyte 13 0e0000h - 0effffh 64 kbyte 12 0d0000h - 0dffffh 64 kbyte 11 0c0000h - 0cffffh 64 kbyte 10 0b0000h - 0bffffh 64 kbyte 9 0a0000h - 0affffh 64 kbyte 8 090000h - 09ffffh 64 kbyte 7 080000h - 08ffffh 64 kbyte 6 070000h - 07ffffh 64 kbyte 5 060000h - 06ffffh 64 kbyte 4 050000h - 05ffffh 64 kbyte 3 040000h - 04ffffh 64 kbyte 2 030000h - 03ffffh 64 kbyte 1 020000h - 02ffffh 64 kbyte 0 010000h - 01ffffh 64 kbyte t8.0 1359
24 advance information serial quad i/o (s qi) flash memory sst26vf016 / sst26vf032 ?2008 silicon storage technology, inc. s71359-00-000 04/08 table 9: block-protection register for 26vf032 (1 of 2) bpr bits address range protected block size read lock write lock 79 78 3fe000h - 3fffffh 8 kbyte 77 76 3fc000h - 3fdfffh 8 kbyte 75 74 3fa000h - 3fbfffh 8 kbyte 73 72 3f8000h - 3f9fffh 8 kbyte 71 70 006000h - 007fffh 8 kbyte 69 68 004000h - 005fffh 8 kbyte 67 66 002000h - 003fffh 8 kbyte 65 64 000000h - 001fffh 8 kbyte 63 3f0000h - 3f7fffh 32 kbyte 62 008000h - 00ffffh 32 kbyte 61 3e0000h - 3effffh 64 kbyte 60 3d0000h - 3dffffh 64 kbyte 59 3c0000h - 3cffffh 64 kbyte 58 3b0000h - 3bffffh 64 kbyte 57 3a0000h - 3affffh 64 kbyte 56 390000h - 39ffffh 64 kbyte 55 380000h - 38ffffh 64 kbyte 54 370000h - 37ffffh 64 kbyte 53 360000h - 36ffffh 64 kbyte 52 350000h - 35ffffh 64 kbyte 51 340000h - 34ffffh 64 kbyte 50 330000h - 33ffffh 64 kbyte 49 320000h - 32ffffh 64 kbyte 48 310000h - 31ffffh 64 kbyte 47 300000h - 30ffffh 64 kbyte 46 2f0000h - 2fffffh 64 kbyte 45 2e0000h - 2effffh 64 kbyte 44 2d0000h - 2dffffh 64 kbyte 43 2c0000h - 2cffffh 64 kbyte 42 2b0000h - 2bffffh 64 kbyte 41 2a0000h - 2affffh 64 kbyte 40 290000h - 29ffffh 64 kbyte 39 280000h - 28ffffh 64 kbyte 38 270000h - 27ffffh 64 kbyte 37 260000h - 26ffffh 64 kbyte 36 250000h - 25ffffh 64 kbyte 35 240000h - 24ffffh 64 kbyte 34 230000h - 23ffffh 64 kbyte 33 220000h - 22ffffh 64 kbyte 32 210000h - 21ffffh 64 kbyte 31 200000h - 20ffffh 64 kbyte 30 1f0000h - 1fffffh 64 kbyte
advance information serial quad i/o (sqi) flash memory sst26vf016 / sst26vf032 25 ?2008 silicon storage technology, inc. s71359-00-000 04/08 29 1e0000h - 1effffh 64 kbyte 28 1d0000h - 1dffffh 64 kbyte 27 1c0000h - 1cffffh 64 kbyte 26 1b0000h - 1bffffh 64 kbyte 25 1a0000h - 1affffh 64 kbyte 24 190000h - 19ffffh 64 kbyte 23 180000h - 18ffffh 64 kbyte 22 170000h - 17ffffh 64 kbyte 21 160000h - 16ffffh 64 kbyte 20 150000h - 15ffffh 64 kbyte 19 140000h - 14ffffh 64 kbyte 18 130000h - 13ffffh 64 kbyte 17 120000h - 12ffffh 64 kbyte 16 110000h - 11ffffh 64 kbyte 15 100000h - 10ffffh 64 kbyte 14 0f0000h - 0fffffh 64 kbyte 13 0e0000h - 0effffh 64 kbyte 12 0d0000h - 0dffffh 64 kbyte 11 0c0000h - 0cffffh 64 kbyte 10 0b0000h - 0bffffh 64 kbyte 9 0a0000h - 0affffh 64 kbyte 8 090000h - 09ffffh 64 kbyte 7 080000h - 08ffffh 64 kbyte 6 070000h - 07ffffh 64 kbyte 5 060000h - 06ffffh 64 kbyte 4 050000h - 05ffffh 64 kbyte 3 040000h - 04ffffh 64 kbyte 2 030000h - 03ffffh 64 kbyte 1 020000h - 02ffffh 64 kbyte 0 010000h - 01ffffh 64 kbyte t9.0 1359 table 9: block-protection register for 26vf032 (continued) (2 of 2) bpr bits address range protected block size read lock write lock
26 advance information serial quad i/o (s qi) flash memory sst26vf016 / sst26vf032 ?2008 silicon storage technology, inc. s71359-00-000 04/08 lockdown block-protecti on register (lbpr) the lockdown block-protection register instruction pre- vents changes to the block-protection register. lockdown resets after power cycling; this allows the block-protection register to be changed. to execute a lockdown block-protection register, the host rives ce# low, then sends the lockout security id com- mand cycle (8dh), then drives ce# high. a cycle is two nibbles long, most signi ficant nibble first. figure 24: lock-down block protection register 1359 f30.0 mode 3 0 1 sck sio(3:0) ce# c1 c0 mode 0 note: c[1:0]=8dh
advance information serial quad i/o (sqi) flash memory sst26vf016 / sst26vf032 27 ?2008 silicon storage technology, inc. s71359-00-000 04/08 electrical specifications absolute maximum stress ratings (applied conditions greater than t hose listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater t han those defined in the operational sections of this data sheet is not implied. exposu re to absolute maximum stress rating co nditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v package power dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount solder reflow temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds output short circuit current 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. output shorted for no more than one second. no more than one output shorted at a time. o perating r ange range ambient temp v dd commercial 0c to +70c 2.7-3.6v industrial -40c to +85c 2.7-3.6v ac c onditions of t est input rise/fall time . . . . . . . . . . . . . . 3 ns output load . . . . . . . . . . . . . . . . . . . . c l = 30 pf see figure 28
28 advance information serial quad i/o (s qi) flash memory sst26vf016 / sst26vf032 ?2008 silicon storage technology, inc. s71359-00-000 04/08 power-up specifications all functionalities and dc specif ications are specified for a v dd ramp rate of greater than 1v per 100 ms (0v to 2.7v in less than 270 ms). see table 10 and figure 25 for more information. figure 25: power-up timing diagram table 10: recommended system power-up timings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. v dd min to read operation 100 s t pu-write 1 v dd min to write operation 100 s t10.0 1359 time v dd min v dd max v dd device fully accessible t pu-read t pu-write chip selection is not allowed. commands may not be accepted or properly interpreted by the device. 1359 f27.0
advance information serial quad i/o (sqi) flash memory sst26vf016 / sst26vf032 29 ?2008 silicon storage technology, inc. s71359-00-000 04/08 dc characteristics table 11: dc operating characteristics (v dd = 2.7- 3.6v) symbol parameter limits test conditions min typ max units i ddr read current 12 18 ma ce#=0.1 v dd /0.9 v dd @80 mhz, so=open i ddw program and erase current 30 ma ce#=v dd i sb1 standby current 8 15 a ce#=v dd , v in =v dd or v ss i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 1 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ih input high voltage 0.7 v dd vv dd =v dd max v ol output low voltage 0.2 v i ol =100 a, v dd =v dd min v oh output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min t11.0 1359 table 12: capacitance (ta = 25c, f=1 mhz, other pins open) parameter description test condition maximum c out 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. output pin capacitance v out = 0v 12 pf c in 1 input capacitance v in = 0v 6 pf t12.0 1359 table 13: reliability characteristics symbol parameter minimum spec ification units test method n end 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. endurance 100,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t13.0 1359
30 advance information serial quad i/o (s qi) flash memory sst26vf016 / sst26vf032 ?2008 silicon storage technology, inc. s71359-00-000 04/08 ac characteristics figure 26: serial input timing diagram table 14: ac operating characteristics symbol parameter limits - 33 mhz limits - 80 mhz units min max min max f clk serial clock frequency 33 80 mhz t clk serial clock period 30 12.5 ns t sckh serial clock high time 13 5.5 ns t sckl serial clock low time 13 5.5 ns t sckr 1 1. maximum rise and fall time may be limited by t sckh and t sckl requirements serial clock rise time (slew rate) 0.1 0.1 v/ns t sckf 1 serial clock fall time (slew rate) 0.1 0.1 v/ns t ces 2 2. relative to sck. ce# active setup time 12 3 ns t ceh 2 ce# active hold time 12 3 ns t chs 2 ce# not active setup time 10 3 ns t chh 2 ce# not active hold time 10 3 ns t cph ce# high time 100 12.5 ns t chz ce# high to high-z output 14 12.5 ns t clz sck low to low-z output 0 0 ns t ds data in setup time 3 2 ns t dh data in hold time 3 3 ns t oh output hold from sck change 0 0 ns t v output valid from sck 12 5 ns t se sector-erase 25 25 ms t be block-erase 25 25 ms t sce chip-erase 50 50 ms t pp page-program 1.3 1.3 ms t psid program security id 0.2 0.2 ms t ws write-suspend latency 10 10 s t14.1 1359 ce# sio sck msb lsb t ds t dh t chh t ces t ceh t chs t sckr t sckf t cph 1359 f24.0
advance information serial quad i/o (sqi) flash memory sst26vf016 / sst26vf032 31 ?2008 silicon storage technology, inc. s71359-00-000 04/08 figure 27: serial output timing diagram figure 28: reset timing diagram figure 29: ac input/output reference waveforms table 15: reset ti ming parameters t r(i) parameter minimum maximum units t r(o) reset to read (non-data operation) 10 ns t r(p) reset recovery from program or suspend 50 s t r(e) reset recovery from erase 1 ms t15.0 1359 1359 f25.0 ce# sio sck msb t clz t v t sckh t chz t oh t sckl lsb 1359 f14.0 mode 3 clk sio(3:0) ce# mode 3 c1 c3 c2 c0 mode 0 mode 3 mode 0 mode 0 t ceh note: c[1:0] = 55h; c[3:2] = aah 1359 f28.0 reference points output input v ht v lt v ht v lt v iht v ilt ac test inputs are driven at v iht (0.9v dd ) for a logic ?1? and v ilt (0.1v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v ht (0.6v dd ) and v lt (0.4v dd ). input rise and fall times (10% ? 90%) are <3 ns. note: v ht - v high te s t v lt - v low te s t v iht - v input high test v ilt - v input low test
32 advance information serial quad i/o (s qi) flash memory sst26vf016 / sst26vf032 ?2008 silicon storage technology, inc. s71359-00-000 04/08 product ordering information valid combinations for sst26vf016 sst26vf016-80-5c-qaf SST26VF016-80-5C-S2AF sst26vf016-80-5i-qaf sst26vf016-80-5i-s2af valid combinations for sst26vf032 sst26vf032-80-5c-qaf sst26vf032-80-5c-s2af sst26vf032-80-5i-qaf sst26vf032-80-5i-s2af note: valid combinations are those products in mass producti on or will be in mass production. consult your sst sales representative to confirm availability of valid combinat ions and to determine availability of new combinations. sst 26 vf 32 - 80 - 5c - s2a f xx x xxx -xx -xx -xxx x environmental attribute f 1 = non-pb / non-sn contact (lead) finish package modifier a = 8 leads or contacts package type q = wson (6 mm x 5 mm) s2 = soic (200 mil body width) temperature range c = commercial = 0c to +70c i = industrial = -40c to +85c minimum endurance 5 = 100,000 cycles operating frequency 80 = 80 mhz device density 16 = 16 mbit 32 = 32 mbit voltage v = 2.7-3.6v product series 26 = serial quad i/o (sqi) flash memory 1. environmental suffix ?f? denotes non-pb/non-sn solder. sst non-pb/non-sn solder devi ces are ?rohs compliant?.
advance information serial quad i/o (sqi) flash memory sst26vf016 / sst26vf032 33 ?2008 silicon storage technology, inc. s71359-00-000 04/08 packaging diagrams figure 30: 8-contact very-very-thin, small-outline, no-lead (wson) sst package code: qa note: 1. all linear dimensions are in millimeters (max/min). 2. untoleranced dimensions (shown with box surround) are nominal target dimensions. 3. the external paddle is electrically connected to the die back-side and possibly to certain v ss leads. this paddle can be soldered to the pc board; it is suggested to connect this paddle to the v ss of the unit. connection of this paddle to any other voltage potential can result in shorts and/or electrical malfunction of the device. 8-wson-5x6-qa-9.0 4.0 1.27 bsc pin #1 0.48 0.35 0.076 3.4 5.00 0.10 6.00 0.10 0.05 max 0.70 0.50 0.80 0.70 0.80 0.70 pin #1 corner top view bottom view cross section side view 1mm 0.2
34 advance information serial quad i/o (s qi) flash memory sst26vf016 / sst26vf032 ?2008 silicon storage technology, inc. s71359-00-000 04/08 figure 31: 8-lead, small outlin e integrated circuit (soic) sst package code: s2a table 16: revision history number description date 00 ? initial release of data sheet apr 2008 2.16 1.75 08-soic-eiaj-s2a-3 note: 1. all linear dimensions are in millimeters (max/min). 2. coplanarity: 0.1 mm 3. maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads. top view side view end view 5.40 5.15 8.10 7.70 5.40 5.15 pin #1 identifier 0.50 0.35 1.27 bsc 0.25 0.05 0.25 0.19 0.80 0.50 0? 8? 1mm silicon storage technology, inc. ? 1171 sonora court ? sunnyvale, ca 94086 ? telephone 408-735-9110 ? fax 408-735-9036 www.superflash.com or www.sst.com

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